1. Field of the Invention
The present invention relates to a pattern transfer mask for use in manufacture of a semiconductor device including dual damascene structures, and further relates to a method of manufacturing a semiconductor device using the pattern transfer mask.
2. Description of the Background Art
Copper (Cu) dual damascene structures have conventionally been employed for multilevel interconnection for semiconductor devices. Such structures are formed as described below. First, via holes are formed in an oxide film of a substrate. Thereafter, resist is coated entirely over the oxide film, and is patterned into a pattern that corresponds to trenches by exposure to light and development. An anti-reflection film may be deposited by coating or the like before coating resist for via holes or trenches. Next, the oxide film is etched using the patterned resist as a mask, thereby forming trenches. The trenches are formed over the via holes. Then, a Cu film is plated in the via holes and trenches, thereby completing a dual damascene structure.
Such dual damascene structure is introduced by Japanese Patent Application Laid-Open No. 2000-58647 (FIG. 4), for example.
With the above-described conventional method, resist is coated entirely over the oxide film in which the via holes are formed or over the anti-reflection film, and thus collects in the via holes. At this time, the thickness of resist (i.e., the thickness based on the surface of part of the oxide film where no via hole is formed) tends to be small over the via holes. Besides, the resist collects in the via holes in different manners depending on the layout of the via holes. Thus, the resist varies in thickness in an area where no via hole is formed, an area where many via holes are opened and an area where less via holes are opened.
Likewise, in the case where the anti-reflection film is deposited by coating on the oxide film in which via holes are formed, the anti-reflection film varies in thickness depending on the layout of the via holes.
If resist varies in thickness in light transfer, a finished dimension of a resist pattern after development varies due to standing wave effect (interference effect) and bulk effect (absorbing effect) even with the same amount of exposure. That is, a problem arises in that a trench pattern of a desired dimension cannot be obtained resulting from the presence and layout of via holes.
Likewise, when the anti-reflection film varies in thickness, a trench pattern of a desired dimension cannot be obtained resulting from variations in reflectance.
Further, exposure light generally varies in reflectance in an area where via holes are present and an area where via holes are absent, which causes effective exposure to vary even with the same amount of exposure. In this case, a trench pattern of a desired dimension cannot be obtained, similarly to the above-described cases.
As a result of the above-described drawback, if finished trenches are narrower than desired, increase in wiring resistance and breaks easily occur. Conversely, if finished trenches are wider than desired, wiring resistance becomes lower than a design value and adjacent interconnect lines are short-circuited. That is, designed operations cannot be obtained in semiconductor devices.